Electromigration in PCBs: Design Techniques to Minimize CAF, Dendrites, and Metallic Migration
Electromigration is often discussed as though it were a single failure mechanism. In printed circuit boards, however, several electrically assisted transport mechanisms can produce similar symptoms: rising leakage, intermittent shorts, unexpected resets, and ultimately open or short circuits. A robust design approach begins by separating them.
Classical electromigration is movement of metal atoms driven by electrical current density, often associated with high-current interconnects, localized heating, void formation, and eventual opens. Electrochemical migration (ECM) is different: moisture and ionic contamination create an electrolytic path between conductors, allowing metal to dissolve, move as ions, and redeposit as dendrites. Conductive anodic filament formation (CAF) is an internal laminate failure in which copper filaments grow through resin-glass structures between biased conductors. These mechanisms can interact, but their design controls are not identical.
The paper A Review of Models for Time-to-Failure Due to Metallic Migration Mechanisms by Elissa Bumiller and Dr. Craig Hillman is useful because it treats metallic migration as a physics-of-failure problem rather than merely a pass/fail cleanliness test. Its central lesson is practical: temperature, humidity, voltage, electric-field strength, spacing, contamination, conductor material, laminate construction, and process history all influence risk.
First, distinguish the failure mechanisms
Surface ECM occurs when a thin moisture film forms between adjacent conductors. Under DC bias, metal can dissolve at one conductor, enter the moisture layer as positive ions, travel through the electrolyte, and reduce at the oppositely biased conductor. Repeated deposition produces a dendrite, a fragile tree-like metallic bridge that can suddenly reduce surface insulation resistance.
Dendrites are troublesome because they can be intermittent. A small dendrite may heat locally and burn open when current flows through its narrow cross-section. Resistance then recovers, only for migration to begin again. This behavior can create “no trouble found” or “could not duplicate” failures during service or laboratory troubleshooting.
CAF is an internal, bulk phenomenon. Copper migrates through the printed-circuit laminate, commonly along resin-glass interfaces or damaged pathways between plated holes, vias, or traces. CAF risk is affected by laminate material, glass-weave geometry, resin chemistry, moisture absorption, drilling quality, hole-wall integrity, conductor spacing, and applied electric field.
Classical current-driven electromigration is a third category. Electron flow transfers momentum to metal atoms. High current density, elevated temperature, material defects, and current crowding can move atoms away from one region and accumulate them in another. The result may be voids, hillocks, local resistance growth, or open circuits. This mechanism is more familiar in semiconductor metallization, but PCB traces, plated structures, solder joints, and fine interconnects can also experience current-density-related degradation.
The common thread is that electrical stress supplies the driving force, while temperature, moisture, materials, geometry, and defects determine how quickly damage develops.
What the metallic-migration theory says
Bumiller and Hillman describe ECM in three stages: path formation, initiation, and dendritic growth. Path formation is creation of an electrolytic medium, often by water molecules adsorbing to the board surface. Initiation includes electrodissolution at one conductor, ion transport through the electrolyte, and electrodeposition at the opposite conductor. The final stage is growth of the dendrite back toward the source conductor.
This sequence explains why a clean, dry board can tolerate a voltage that becomes dangerous after contamination or condensation. Without moisture, ionic transport is limited. Without contamination, the surface film has lower conductivity and the metal supply may be insufficient. Without a voltage gradient, there is no strong directional force to move ions across the gap.
The paper reviews several time-to-failure models. The Arrhenius model represents temperature acceleration through an activation-energy relationship. It is useful, but temperature alone cannot describe ECM because it omits humidity, voltage, contamination, and their interactions.
The Eyring model extends the concept by adding stresses such as humidity and voltage. It is more realistic conceptually, but every added stress introduces unknown coefficients and an assumed stress function. Other models focus on dendrite growth, corrosion, or conductive filament formation. A recurring insight is that voltage gradient—approximately voltage divided by conductor spacing—can be more fundamental than voltage alone. At the same voltage, reducing spacing increases the electric field. Smaller gaps also hold contamination more effectively and are harder to clean.
The paper also highlights critical stress thresholds. ECM may not initiate until sufficient surface moisture is present. The discussion cites a critical moisture layer on the order of approximately 20 monolayers, while condensation below the dew point can create a much more conductive path almost immediately. A simple linear extrapolation from a mild test condition can therefore be misleading.
Finally, the rate-limiting step is not always the same. In one design, path formation may dominate. In another, ion transport or dendrite growth may dominate. For CAF, the limiting process may involve moisture penetration and filament growth through the laminate. A universal time-to-failure equation should therefore not replace material-specific testing and failure analysis.
Design techniques that reduce migration risk
1. Control electric field, not just nominal voltage
Reduce the electric field between conductors by increasing creepage and clearance wherever practical, especially between DC-biased nets, high-impedance nodes, battery domains, and conductors exposed to condensation or contamination.
Do not use the minimum spacing from a generic design table without considering the actual environment. A high voltage difference across a narrow gap creates a larger field than the same gap at low voltage. Review connector transitions, test points, via fields, component pads, solder-mask openings, and regions where copper geometry creates local field enhancement.
Avoid sharp copper points and acute corners on biased conductors. Rounded pad entries and smooth trace transitions reduce local field concentration. Keep exposed copper edges controlled after etching and plating; burrs, nicks, and roughness can become preferred sites for ionization or dendrite nucleation.
2. Prevent moisture films and condensation
Moisture is part of the electrical circuit in ECM. Use enclosure, venting, drainage, sealing, and thermal design to prevent water from remaining on the board. Analyze cold-start and shutdown conditions, because a board may cross the dew point even when steady-state ambient temperature looks acceptable.
Conformal coating can reduce surface moisture access, but it is not a substitute for sound layout or cleaning. Coverage must include the critical regions, and the process must control bubbles, voids, delamination, pinholes, residues trapped beneath the coating, and compatibility with components and solder joints. Masking and component shadows can create uncoated paths that defeat the barrier.
Where the board is exposed to condensation, evaluate solder-mask integrity, coating permeability, surface energy, and water adsorption behavior. The paper notes that solder-mask choice and surface contamination influence the amount of water adsorbed to the PCB, so material selection and process cleanliness are coupled decisions.
3. Make cleanliness a design requirement
Halide contamination, particularly chloride and bromide species, is among the most important ECM accelerants. Residues can increase surface conductivity, lower the humidity threshold for water adsorption, and provide mobile ions for transport. A “no-clean” process is not automatically a clean process; residue chemistry, reflow profile, geometry, and environmental exposure determine whether the remaining material is benign.
Define cleanliness requirements for the assembled product, not only the bare board. Specify flux controls, paste and adhesive controls, handling, wash chemistry, rinse quality, drying, ionic cleanliness measurements, and acceptance criteria. Review areas that are difficult to clean, including fine-pitch packages, bottom-terminated components, shield edges, underside cavities, via-in-pad structures, and stiffeners.
Use surface insulation resistance testing and ionic contamination analysis as process controls, but correlate results with the actual design and environment. A single bulk cleanliness number may not reveal a localized residue next to a high-field conductor.
4. Design the stackup and laminate for CAF resistance
CAF prevention starts with understanding the internal electric field and moisture path. Increase spacing between biased plated holes and vias, especially when structures are aligned along a glass-weave channel. Avoid unnecessarily long parallel runs of closely spaced vias or traces in moisture-sensitive regions.
Select laminate materials using CAF-resistance data relevant to the intended voltage, temperature, humidity, and construction. Evaluate resin content, glass style, weave spread, moisture absorption, Z-axis properties, and fabrication compatibility. Good nominal material data cannot compensate for poor drilling, desmear, lamination, or hole-wall quality.
Control drill registration and hole-wall quality. Rough or damaged hole walls, resin recession, glass protrusion, voids, and inadequate desmear can create initiation sites or shorten the effective migration path. For safety-critical or high-humidity applications, perform CAF testing on representative stackups rather than relying only on supplier datasheets.
5. Manage conductor materials and finishes
Conductor material affects electrochemical potential and migration behavior. The paper notes that copper, nickel, silver, gold, and solder materials do not behave identically. ENIG can be relatively resistant while the gold remains intact, but damage that exposes nickel can change local behavior. Immersion silver deserves attention in humid environments because silver compounds can participate in migration, although modern chemistries may be more resistant than older formulations.
The design rule is not that one finish is universally safe. Understand which material is exposed after assembly, which areas remain exposed after reflow, whether solder mask is intact, and how scratches, porosity, corrosion, or process variation change the surface. Finish selection should be evaluated together with spacing, contamination, humidity, and bias.
6. Reduce current crowding for classical electromigration
For current-driven electromigration, increase trace width and copper thickness where current density is high. Avoid abrupt neck-downs, sharp corners, isolated thermal bottlenecks, and narrow vias carrying substantial current. Use parallel vias or multiple current paths where appropriate, and verify current sharing rather than assuming it.
Use thermal simulation or measurement to identify hot spots. Because atomic transport accelerates with temperature, a small region of current crowding can become the dominant lifetime limiter even when average trace current appears acceptable. Check solder-joint lands, connector pins, fuse links, shunts, via transitions, and copper constrictions—not only the main trace width.
7. Treat design rules as a system
Spacing, material, cleanliness, coating, voltage, and temperature interact. Increasing one margin may not compensate for a severe weakness in another. For example, conformal coating may reduce surface moisture while contaminated residue remains trapped beneath it. A wide trace may reduce current density while a narrow adjacent gap still creates high ECM risk.
Use a risk-based design review to identify the highest-risk conductor pairs, worst-case voltage state, worst-case humidity and dew-point condition, most difficult-to-clean regions, and most vulnerable internal geometry. Verify that the resulting controls are measurable in production.
Validation and failure analysis
Qualification testing should reproduce the actual mechanism. Surface insulation resistance testing under temperature, humidity, and bias can reveal ECM susceptibility, but the profile, board cleanliness, spacing, bias polarity, and monitoring method must be documented. CAF testing should use representative laminate construction, hole geometry, voltage, and environmental exposure. High-current structures require current-density and thermal validation in addition to surface migration testing.
When a failure occurs, inspect both the surface and the cross-section. Look for dendritic bridges, residue patterns, corrosion products, copper filaments, glass-resin interface damage, hole-wall defects, plated-through-hole cracks, and evidence of condensation. Record the failure state before cleaning or rework; washing the board may remove the evidence that explains the failure.
Use microscopy, cross-sectioning, ion chromatography, surface insulation resistance data, and material analysis as appropriate. Intermittent behavior should increase suspicion, not reduce it. A dendrite that burns open can leave behind little visible evidence while still explaining the original failure.
Practical PCB electromigration checklist
Identify whether the dominant risk is classical current-driven electromigration, surface ECM, CAF, or a combination.
Calculate worst-case voltage gradient using actual biased spacing, not only nominal net classes.
Review creepage, clearance, via-to-via spacing, pad geometry, and exposed copper edges.
Analyze condensation and dew-point crossings over the complete mission profile.
Set measurable ionic cleanliness and residue-control requirements.
Select laminate and finish materials using mechanism-specific reliability data.
Review drilling, registration, desmear, plating, solder-mask, and coating capability.
Reduce current crowding with wider copper, adequate thickness, parallel vias, and smooth transitions.
Validate with representative environmental, SIR, CAF, thermal, and current-density testing.
Preserve physical evidence and perform mechanism-focused failure analysis.
Conclusion
The most reliable PCB is not created by a single spacing rule or a generic “no-clean” label. It is created by controlling the conditions that make metal mobile: electrical field, current density, temperature, moisture, ionic contamination, material chemistry, and defect pathways.
The metallic-migration theory reviewed by Bumiller and Hillman provides a useful framework for making those controls concrete. Migration requires a path, a driving force, a source of mobile species, and a sequence of electrochemical or atomic transport processes. Good PCB design removes or weakens those links before the product reaches the field.
For surface dendrites, prioritize cleanliness, moisture control, voltage-gradient reduction, exposed-material selection, and robust insulation. For CAF, prioritize laminate construction, internal spacing, drill and hole-wall quality, and representative testing. For classical electromigration, prioritize current-density distribution and thermal control. When these mechanisms are separated, modeled with appropriate caution, and validated under realistic conditions, electromigration risk becomes a design variable that can be managed rather than a failure discovered late in qualification.
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